The present invention relates to a semiconductor device provided with tamper resistance for protecting secret information inside the semiconductor device against an act of analysis by fraudulent means.
In recent years, a significantly high degree of secrecy/concealment has been increasingly required for circuit information and inside information of semiconductor devices. In particular, semiconductor devices in the field of IC cards, which are characterized in their safety, are required to protect important information therein against being subjected to fraudulent analysis and prevent inside information from being tampered or copied. In increasing cases, methods for attaining such strict protection functions have been instituted. Related prior art will be described.
FIG. 9 shows a conventional structure of a semiconductor device, which includes a p- or n-substrate 1, a p- or n-well 2, a diffusion isolation layer 3, a transistor element formation portion 4, an insulating layer 5, signal wiring 6 to be protected, defensive wiring 7 and via contacts 8. The defensive wiring 7 is provided for protecting the signal wiring 6 against an act of analysis by fraudulent means. In general, the defensive wiring 7 is placed to cover the signal wiring 6 and may be formed from a plurality of wiring layers. The defensive wiring 7 has such a structure that makes it difficult to observe the layout pattern of the semiconductor device from the front and necessitates peeling or partial cutting of the defensive wiring 7 to reach the signal wiring 6 if analysis of the signal wiring 6 is attempted.
Generally, in a semiconductor device having a structure as described above, some pattern signal is applied at a start point of the defensive wiring 7, and simultaneously a comparison reference signal is supplied to lower-layer wiring of the defensive wiring 7, to compare the two signals at an end point of the defensive wiring 7. If the defensive wiring 7 is peeled or cut, the pattern signal does not reach a comparator, causing a difference in the comparison result. As a result, an abnormal detection signal is issued. With this abnormal detection signal, a means of protecting secret information therein operates (see Japanese National Phase PCT Laid-Open Patent Publication No. 2002-529928 (FIGS. 1 and 3), for example).
The conventional semiconductor device described above assumes fraudulent analysis means such as observation, probing, FIB machining and the like from the front, and therefore is highly tamper-resistant against acts of analysis from the front. However, with the progress of the recent FIB machining technology, there has begun to spread a technology of executing FIB machining from the back of a semiconductor device to reach target wiring and drawing a pad for probing up to the back of the semiconductor device.
FIG. 10 shows a state in which an analysis pad terminal has been drawn out by FIB machining from the back of the semiconductor device. Referring to FIG. 10, in the semiconductor device including the p- or n-substrate 1, the p- or n-well 2, the diffusion isolation layer 3, the Tr element formation portion 4, the insulating layer 5, the signal wiring 6 to be protected, the defensive wiring 7, and the via contacts 8, an insulating layer 9 and an analysis pad terminal 100 are formed by FIB machining. The reference numeral 111 denotes a signal line of which analysis is intended.
First, the p- or n-substrate 1 is cut from the back surface up to a portion near the boundary between the p- or n-substrate 1 and the p- or n-well 2. A hole is then dug in the p- or n-well 2 toward the target signal line 111 placed above the diffusion isolation layer 3 by FIB machining. The insulating layer 9 is formed on the resultant hole, and then the analysis pad terminal 100 is drawn up to the back surface. The conventional semiconductor device described above is no more tamper-resistant at all against fraudulent analysis making full use of such a machining technique.